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    • 专利摘要:
    Object (TG) capable of communicating without contact with a reader (RD) by active load modulation, configured to receive a first carrier signal (clex) emitted by the reader (RD) and deliver a second carrier signal (OUT) , the object comprising synchronization means (MSYNC) configured to synchronize a first carrier signal (clex) and the second carrier signal (OUT), said synchronization means (MSYNC) comprising detection means (MD) configured to detecting the locking of said loop (DPLL), and control means (MC) configured to slave the frequency of the output signal of an oscillator (DCO) by controlling the oscillator (DCO) with a first control signal (VAL1 ) generated from a first value (ERR1) representative of the phase error of said phase locked loop (DPLL), then with a second control signal (VAL2) generated from a second value (ERR2 ) issued p ar a first module (MD1) configured to perform an operation of the modulo type on said first value (ERR1) representative of the phase error of the loop.
    公开号:FR3086476A1
    申请号:FR1858732
    申请日:2018-09-25
    公开日:2020-03-27
    发明作者:Marc Houdebine
    申请人:STMicroelectronics SA；
    IPC主号:
    专利说明:

    Fast synchronization between an object and a contactless reader by active load modulation
    Embodiments and embodiments of the invention relate to wireless or contactless communication using contactless devices or electronic components connected to an antenna, in particular devices configured to exchange information with a reader via said antenna according to a communication protocol of the contactless type.
    Embodiments and embodiments of the invention relate more particularly to contactless communication between a contactless device and a reader at a frequency of 13.56 MHz using active load modulation (ALM: "Active Load Modulation" for communication with the reader and more particularly the synchronization between a reader carrier signal and a carrier signal generated within the device (ALM carrier clock signal).
    These contactless components or devices can be, for example, so-called "NFC" components or devices, that is to say devices compatible with NFC ("Near Field Communication") technology.
    The NFC device can for example be an integrated circuit or a chip incorporating an NFC microcontroller.
    The acronym NFC designates a short distance high frequency wireless communication technology, which allows data exchange between two contactless devices over a short distance, for example 10 cm.
    NFC technology is an open technological platform standardized in ISO / IEC 18092 and ISO / IEC 21481 but incorporates many already existing standards such as type A and type B protocols defined in ISO-14443 which can be protocols of communication usable in NFC technology.
    In addition to its traditional telephone function, a cellular mobile telephone can be used (if it is equipped with specific means) to exchange information with another contactless device, for example a contactless reader, using a contactless communication protocol. usable in NFC technology.
    We can also cite other contactless devices such as a connected watch.
    This allows information to be exchanged between the contactless reader and secure items located in the mobile phone. Many applications are thus possible such as mobile ticketing in public transport (the mobile phone behaves like a transport ticket) or else mobile payment (the mobile phone behaves like a payment card).
    When transmitting information between a reader and an emulated object in label or card mode, the reader generates a magnetic field via its antenna which is generally in the standards conventionally used, a sine wave at 13.56 MHz. The strength of the magnetic field is between 0.5 and 7.5 amps / meter RMS ("Root Mean Square" in English).
    Two operating modes are then possible, a passive mode or an active mode.
    In passive mode, only the reader generates the magnetic field and the object, emulated in label or card mode, is then passive and always plays the role of the target.
    More specifically, the antenna of the object emulating the label or the card modulates the field generated by the reader.
    This modulation is carried out by modifying the load connected to the terminals of the object's antenna.
    By changing the load across the object’s antenna, the reader's antenna output impedance changes due to the magnetic coupling between the two antennas. This results in a change in the amplitudes and / or phases of the voltages and currents present at the antennae of the reader and of the object.
    And, in this way, the information to be transmitted from the object to the reader is transmitted by load modulation to the antenna currents of the reader.
    The charge variation carried out during the load modulation results in amplitude and / or phase modulation of the signal (voltage or current) at the antenna of the reader. A copy of the antenna current is generated and injected into the reception chain of the reader where this current is demodulated and processed so as to extract the information transmitted.
    In the active operating mode, the reader and the object emulated in card mode both generate an electromagnetic field. Generally, this mode of operation is used when the object is provided with its own power source, for example a battery, as is the case in a cellular mobile telephone which is then emulated in card mode.
    Each of the NFC devices transmits data using a modulation scheme.
    Again, the modulation results in a load modification and this is called communication by active load modulation.
    Compared to a passive communication mode, we obtain greater operating distances which can be up to 20 cm depending on the protocol used.
    In addition, the use of active load modulation makes it possible to use very small antennas.
    However, this type of active load modulation communication poses other problems.
    Indeed, during the periods of active communication of the device emulated in card mode, the electromagnetic field of the reader is not directly observable. And this can lead to a response from the object emulated in non-synchronous card mode and therefore to a signal received by the reader having a phase shift, in particular during long periods of emission by the device emulated in card mode.
    This is all the more observable when the device emulated in card mode realizes a digital modulation of BPSK type (Binary phase-shift Keying) and transmits information to the reader using the communication protocol of type B at a speed of 848 kbps.
    In addition, for a phase locked loop to be stable, it is recommended to use a fixed frequency. To do this, we restore at best a few pulses of the signal received over a series of pulses. The received signal can therefore have a frequency up to 32 times lower, thus limiting the bandwidth of the phase locked loop. This limitation leads to instabilities at the system level.
    Also, when device emulated in card mode performs Manchester coding to transmit information to the reader and uses the type A communication protocol at a speed of 106 Kbits / s, this leads to a phase shift.
    If we consider two independent devices, namely the reader and an object emulated in card mode, capable of communicating without contact by active load modulation, there is therefore a need to minimize or even eliminate this phase shift.
    According to one aspect, there is provided a method of contactless communication between an object and a reader using active load modulation, the method comprises synchronization between a first carrier signal emitted by the reader and having a reference frequency for example 13.56 MHz, and a second carrier signal drawn from the output signal of an oscillator controlled by a digital phase locked loop of said object, said synchronization comprises:
    as long as a locking of said loop has not been detected, a control of the frequency of the output signal of the oscillator to a frequency multiple of the reference frequency, by controlling the oscillator with a first control signal generated from a first value representative of the phase error of said phase locked loop, and once said lock detected, a continuation of the servo control by controlling the oscillator with a second control signal generated from a second value obtained by an operation of the modulo type carried out on said first value representative of the phase error of the loop.
    The control can be a frequency control or a frequency and phase control.
    It will be noted here that a frequency multiple of the reference frequency is understood in the broad sense, that is to say that said multiple frequency is equal to k times the reference frequency with k greater than or equal to 1.
    Furthermore, it can be considered for example that the locking of the loop is detected if the phase error is less in absolute value than a threshold.
    Those skilled in the art will be able to choose the value of this threshold according to the application and / or the characteristics of the loop.
    This being by way of nonlimiting example, we can take a threshold equal to about 30 degrees at 13.56 MHz.
    By “first carrier signal” is meant for example a clock signal which will be generated and injected into the reception and transmission chain of the emulated object in card mode.
    By "second carrier signal" is meant for example a clock signal which will be generated and injected into the reception and transmission chain of the reader. Said second signal also has the same reference frequency for performing synchronous communication.
    The oscillator is controlled by a first control signal, typically a digital control word, for the purpose of generating said second carrier signal whose frequency is proportional to said first control signal applied to its input. However, said first control signal, when the problems described above appear, impacted by said first value representative of the phase error, makes it difficult or even impossible to converge the phase locked loop, leading to instabilities. This is why, the oscillator is advantageously controlled by said second control signal generated by said second value representative of the error.
    Said second value representative of the error is much lower than said first value thanks to the modulo type operation on said first value. This allows the phase locked loop to converge quickly and reduces phase drifts.
    The second value representative of the error can only be generated after locking the phase locked loop. Indeed, the modulo type operation can lead to phase jumps before said locking. This is why the modulo type operation is advantageously activated only after the detection of said locking.
    As indicated above, the oscillator can deliver a signal having a frequency equal to k times (with k strictly greater than 1) the reference frequency, for example a frequency of 867.84 MHz or else said reference frequency itself. In the case where k is strictly greater than 1, this frequency will then be divided so as to obtain said reference frequency and thus allow synchronization between the reader and the object emulated in card mode.
    Of course if the signal has said reference frequency (k = 1) said frequency will not be divided.
    It should also be noted that the phase-locked loop is digital, advantageously allowing stabilization of the loop, even with a high phase margin, for example greater than 50 °.
    According to one embodiment, said first value is a digital word comprising a first sequence of bits, and said modulo-type operation comprises a selection of least significant bits representing a second sequence of bits representative of said second value.
    The modulo type operation considerably reduces said first value representative of the phase error of the loop, thus leading to a second value. For example, if the first value is 67, the phase-locked loop will seek to reduce the said error and it may take time before it succeeds in making the loop converge to 0. The modulo type operation in this case includes for example selecting the least significant bits, for example “0000011” corresponding to 3, from the first sequence which is “1000011” corresponding to 67. The error is therefore 3.
    This operation is repeated to make the phase error tend towards 0 and thus make the phase locked loop converge quickly.
    According to one mode of implementation, the method comprises, prior to the servoing by said loop, a masking and / or a multiplication of the frequency of the first carrier signal by a mask and / or a multiplying factor.
    Masking the frequency of a digital signal is like masking certain periods of the signal and can therefore amount to division of the frequency.
    The stability of the phase locked loop is independent of the frequency of the first carrier signal thanks to the modulo type operation. We can therefore multiply the frequency of the first carrier signal by a multiplying factor to allow the device emulated in card mode to operate on the rising and falling edges of the first carrier signal.
    Depending on the needs of the system and its components, for example the antenna and its quality coefficient, the frequency of the first carrier signal can be masked by a mask.
    It should be noted that only one of the two operations can be carried out or carried out consecutively.
    According to one mode of implementation, the mask or the multiplicative factor is adjustable.
    The mask or the multiplicative factor can be chosen by a state machine according to different parameters, for example the quality factor of the antenna.
    You can also choose to have a fixed multiplicative factor.
    According to another aspect, an object is proposed capable of communicating without contact with a reader by active load modulation, comprising an input for receiving a first carrier signal emitted by the reader, an output for delivering a second carrier signal drawn an output signal from an oscillator controlled by a digital phase locked loop, and synchronization means configured to synchronize said first carrier signal and the second carrier signal, said synchronization means comprise:
    detection means configured to detect the locking of said loop;
    control means configured for, as long as the detection means have not detected the locking of said loop, slaving the frequency of the oscillator output signal to a frequency multiple of the reference frequency, by controlling the oscillator with a first control signal generated from a first value representative of the phase error of said phase locked loop, and once the detection means have detected said lock, continue the control by controlling the oscillator with a second control signal generated from a second value delivered by a first module configured to perform an operation of the modulo type on said first value representative of the phase error of the loop.
    According to one embodiment, the first value is a digital word comprising a first sequence of bits, and in which said first module is configured to perform said operation by selecting least significant bits representing a second sequence of bits representative of said second value .
    According to one embodiment, the synchronization means comprise a second module configured to mask the frequency of the first carrier signal by a mask prior to slaving by said loop, and a third module configured to multiply the frequency of the first carrier signal by a multiplicative factor prior to enslavement by said loop.
    The third module can be of conventional structure or can for example comprise a frequency doubler described in the French patent application filed under the number 1752114.
    According to one embodiment, the division factor or the multiplicative factor is adjustable.
    According to one embodiment, the phase locked loop comprises an integral proportional type filter configured to filter said first value representative of the phase error and said second value representative of the phase error.
    The object may for example be a cellular mobile phone emulated in card mode.
    Other advantages and characteristics of the invention will appear on reading the detailed description of modes of implementation and embodiments, in no way limiting, and the appended drawings in which:
    Figures 1 to 3, 4A, 4B, 4C, 5 and 6 schematically illustrate different modes of implementation and embodiment of the invention.
    In FIG. 1, the reference TG designates an object, for example a cellular mobile telephone comprising an ANTI antenna for telephone communications. Said object is here emulated in card mode and can for example communicate with an RD reader via another ANT2 antenna, for example an inductor coil, by an active load modulation, called MAC (ALM in English for “Active Load Modulation”).
    To communicate with the reader RD, said object TAG comprises synchronization means MSYNC configured to receive by an input terminal 2000 after processing, a first carrier signal CLK having a frequency of 13.56 MHz. This frequency is a reference frequency on which the object TG aims to synchronize using said synchronization means MSYNC, during the communication of said object to the reader RD.
    Said TG object comprises a first MD1 module configured to perform a modulo operation, a second MD2 module configured to mask the frequency of a signal by a mask, and a third MF module, here a frequency multiplier configured to multiply the frequency of a signal by a factor.
    The frequency multiplier MF is configured to receive by its input terminal 98 the first carrier signal CLK and to deliver by its output terminal 99, said first carrier signal CLK whose frequency has been multiplied by a factor, here SIG8 . This signal SIG8 is then delivered to the synchronization means MSYNC by said input terminal 2000.
    Said MSYNC synchronization means comprise said second module MD2 configured to mask by a mask the frequency of said signal SIG8.
    The second module MD2 is controlled by a state machine MA configured to, according to various parameters, for example the coefficient of the antenna ANT2, deliver a first control signal CMD1 by its output terminal 3002 to said second module MD2 by its input terminal 3001.
    Said state machine MA is also configured to deliver a second control signal CMD2 via its output terminal 3003 to an input terminal 3000 of the frequency multiplier MF.
    An alternative consists in continuously multiplying said frequency by a fixed multiplicative factor. In this case, said state machine MA is no longer coupled to the frequency multiplier MF.
    Said second module MD2 comprises a register MO configured to store a value SIG3 defined by the control signal CMD1 of the state machine MA. Said second module MD2 also includes a second GAT module configured to receive by its input terminal 10 the signal SIG8, mask it to deliver by its output terminal 11, the clex signal.
    The synchronization means MSYNC comprise a digital phase locked loop DPLL comprising a DCO oscillator controlled by a digital signal (digital word) and configured to receive by its input 1000 said clex signal and to deliver to output 20 of the DCO oscillator a signal SIG4 having a frequency multiple of the reference frequency, for example 64x13.56 MHz.
    Said signal SIG4 is then processed to obtain a second carrier signal OUT having said reference frequency by an output 24.
    To do this, said phase locked loop DPLL comprises an adder-subtractor ST configured to receive said clex signal by its input terminal 30 and to deliver the signal ERR1 by its output terminal 31. The signal ERR1 is a digital signal representative of a first value of the phase error of the phase locked loop.
    Said phase-locked loop DPLL also comprises said first module MD1 configured to receive on its input terminal 32, the signal ERR1 and to deliver by its output terminal 33 the signal ERR2. Said first module MD1 is configured to perform a modulo type operation on the signal ERR1. The result of said operation is the signal ERR2 representative of a second value of the phase error of the loop.
    Said signal ERR2 is then sent to an input terminal 34 of a digital filter DF of said phase-locked loop DPLL, configured to deliver a first control signal VAL1 or a second control signal VAL2 at input 19 of the COD oscillator.
    Advantageously, said digital filter DF can be of the proportional-integral type, which makes it possible to maintain the stability of the loop DPLL thanks to an appropriate choice of the poles of said filter.
    Of course, the skilled person can use any digital filter having the same characteristics. The synchronization means MSYNC also comprise detection means MD configured to detect the locking of the DPLL loop.
    By "locking" is meant the time required for the phase locked loop to catch and stabilize. During this phase, some components of the loop that we will present in Figure 2 are saturated.
    To detect said locking, the phase locked loop DPLL is configured to deliver a signal SIG10 representative of the phase error of the loop, by its output terminal 53, to the input terminal 52 of the detection means MD.
    Said detection means MD are configured to compare said signal SIG10 with a threshold and deliver a signal SIG6 in the high state if the phase error is less in absolute value at said threshold.
    In other words, the loop lock is detected if the SIG6 signal is high.
    Said detection means MD are configured to deliver said signal SIG6 by an output terminal 54 to control means MC by an input terminal 80.
    Said control means MC are configured to deliver a control signal CTRL by an output terminal 81 to an input terminal 56 of the first module MD1. Said control signal CTRL is configured to, depending on its state, deactivate the first module MD1 as long as the loop has not been locked or activate it after locking the DPLL loop so that it performs a modulo operation.
    Another alternative would be a first state allowing a modulo operation to be carried out, for example 8 × 64 during the locking phase of the DPLL loop so as not to alter its operation and a second state making it possible to perform a modulo 64 operation after locking said loop. .
    If said first module MD1 is not activated, it will not perform a modulo operation and the signal ERR1 will be the same as the signal ERR2. In other words, the output terminal 33 of the first module MD1 will deliver the signal ERR1. In this case, the digital filter DF is configured to deliver said first control signal VAL1.
    If said first module MD1 is activated, it will perform said modulo operation and the digital filter DF will deliver by said output 35 the second control signal VAL2.
    Figure 2 shows a detailed view of the DPLL phase locked loop.
    The phase locked loop DPLL comprises an ACC accumulator configured to be clocked by said first carrier signal clex via a first input terminal 12, and also configured to receive by a second input terminal 506 a digital value NI here 64 , and by a third input terminal 36, an accout signal delivered by said accumulator ACC by the output terminal 13.
    Said signal acc out is delivered to the adder-subtractor ST by its input terminal 30 which will deliver by its output terminal 31 the signal ERR1. Said signal ERR1 is received by the input terminal 32 of the first module MD1 which is configured to deliver the signal ERR2 and to be controlled by the signal CTRL delivered by the control means MD.
    Said signal ERR2 is sent to an add adder by its first input terminal 6001. Said add adder is also configured to receive by its second input terminal 6000, the off signal representative of a static phase error in order to compensate phase errors from the matching circuit to the antenna.
    Said add adder is configured to deliver via its output terminal 6002, the signal SIG2 representing the result of the addition between the signal ERR1 and the signal off.
    Said digital filter DF is configured to receive by its input terminal 34 said signal SIG2 and to deliver by its output terminal 35 said first control signal VAL1 or the second control signal VAL2 to input terminal 19 of the DCO oscillator according to the operating mode of the first MD1 module.
    Said DCO oscillator is configured to deliver by its output terminal 20 said signal SIG4 which will be sent to a counter-divider cnt (here a divider by 64) configured to deliver by the output terminal 24 the second carrier signal OUT and to deliver a signal cntout representative of the digital counting result by its output terminal 6003 at an input terminal 60 of the adder-subtractor ST.
    The circuit which has just been described is here advantageously digital since it allows the phase-locked loop to have a phase margin greater than 50 °, which makes it possible to stabilize the loop.
    FIG. 3 schematically illustrates said modulo operation performed by the first module MD1 once activated.
    The signal ERR1 representative of the phase error of the DPLL loop is a signal here composed of 7 bits representing a first unsigned sequence SQ1.
    It is assumed that the signal ERR1 has a value of 67 which is equivalent to a sequence SQ1 of "1000011". The modulo operation consists in selecting the least significant bits PF of said first sequence here "000011" to form a second sequence SQ2 of 7 bits, here "0000011" representing the numerical value 3.
    Said digital value 3 is here the signal ERR2 representative of the phase error of the phase locked loop DPLL.
    The modulo operation therefore makes it possible to greatly reduce said error ERR1 and consequently, the control signal which will be delivered to the DCO oscillator will lead to a slight correction allowing said loop to converge more quickly.
    FIG. 4A schematically illustrates an embodiment of the invention.
    A first graph grl represents the time evolution of the signal acc out delivered by the ACC accumulator and of the signal cnt out delivered by the counter-divider cnt.
    The second graph gr2 represents the temporal evolution of the phase error E equal to the difference between the acc ent signal and the cnt out signal. We can notice that the error E decreases progressively and tends towards 0 in P3 by the action of the phase locked loop DPLL.
    The period PI corresponds to a period of absence of the first carrier signal CLK. The ACC accumulator being clocked by the clex signal extracted from the first carrier signal CLK, is frozen and therefore the accout signal does not change during the period PL
    The cntout signal is clocked by the DCO oscillator and therefore continues to increment. However, the phase error E cannot be calculated because the adder-subtractor ST is also clocked by the signal clex. This is represented by the period P5 of the second graph gr2 where it can be seen that the error E no longer varies during the entire period PI representative of the absence of the first carrier signal CLK.
    Once the first carrier signal is present again, it can be seen that despite the large difference between the acc out and cnt out signals represented by P2, the error E is not significant (P4) and tends to 0. This is due to the modulo operation here modulo 64 which made it possible to significantly reduce the error E and to ensure good phase tracking.
    We can also see that following the saturation of the divisor counter cnt, the error E also tends to 0. The phase locked loop therefore converges more quickly and therefore makes it possible to ensure good phase tracking.
    FIG. 4B represents the time evolution of the behavior of the phase locked loop DPLL according to an embodiment of the invention.
    A first period SI representative of the locking phase of the phase locked loop DPLL takes place during the presence of the first carrier signal CLK.
    Once the loop is locked, said SIG6 signal initially in the low state goes to the high state.
    However, said first carrier signal CLK is then absent during periods FR, which leads after return of the first carrier signal CLK to a jump SA of the phase error E of the phase locked loop due to the offset between cnt out and acc out. Thanks to the action of the modulo, we note that each time the first carrier signal CLK is returned, the phase locked loop DPLL converges quickly, thus avoiding phase drifts.
    The rapid convergence of the phase locked loop DPLL allows the rising edges of the first carrier signal CLK to be aligned with the second carrier signal OUT and therefore the two signals are synchronized.
    FIG. 4C represents the temporal evolution of the behavior of said DPLL loop according to an embodiment of the invention and more precisely in the case of close bursts of responses from the TAG object to the RD reader.
    In this case, the residual energy in the ANT2 antenna after each emission burst limits the duration of the FR periods. The first carrier signal CLK can then be used for a shorter time and consequently the clex signal has a lower frequency. Without the action of the modulo, this leads to phase drifts.
    The action of the modulo allows here after locking (period SI) of said loop DPLL to quickly converge the loop during period S2 and align the rising edges of the first carrier signal CLK and the second carrier signal OUT. Therefore, regardless of the sampling frequency of the first CLK carrier signal, the rising edges of the first CLK carrier signal and the second OUT carrier signal align.
    Figure 5 shows the action of the second MD2 module on the clex signal.
    During a TX data transmission, the data is coded, here by BPSK coding for a transmission by the type B protocol at a speed of 848 kbps and in the case of a bit inversion with each transmission. The coding leads to a first carrier signal CLK comprising, between each pulse, 32 periods of 13.56 MHz.
    Without the action of the modulo and the DF filter which makes it possible to no longer take into consideration the periods of absence of the first carrier signal CLK, the phase-locked loop DPLL can no longer be synchronous with the phase of the RD player at once. by stroke. This leads to a signal having a lower frequency thus limiting the bandwidth of the phase locked loop DPLL, which leads to instabilities.
    To maintain the widest possible bandwidth in order to optimize the noise rejection of the various modules and the variation of the frequency of the phase locked loop DPLL, the correction of the phase error is advantageously made the most possible.
    To do this, it is advantageous to restore the stable periods of the CLK signal extracted from the electromagnetic field of the reader as much as possible even if the CLK signal is not periodic. Thus in this regard, the register MO by sending said signal SIG3 to the second module GAT makes it possible to mask the first carrier signal CLK not every 32 periods but by an optimum value chosen for example 24, 8 or any other value, which broadens the bandwidth of the DPLL phase locked loop.
    The division factor is chosen by said state machine MA as a function of several parameters, for example the quality factor of the antenna ANT2.
    FIG. 6 illustrates a flow diagram representative of an embodiment of the invention.
    Steps E1 to E4 correspond to the period during which the phase-locked loop DPLL tries to lock. For this, the adder-subtractor ST develops, in step E2 said signal ERR1 representative of the first value of the phase error of the loop DPLL, which leads to the generation of the first control signal VAL1 in the step E7.
    Said first control signal VAL1 is then delivered to the DCO oscillator in order to slave it in frequency in step E8.
    Once the loop is locked (step E3), the detection means MD detect said locking by receiving the signal SIG10 and deliver the signal SIG6 in a high state to the control means MC configured to activate said first module MD1 in step E5.
    The ST adder-subtractor continues to deliver the signal
    ERR1 on which the modulo operation will be carried out by the first module MD1 thus delivering the signal ERR2 in step E6 and consequently leading to the generation of the second control signal 5 VAL2 in step E7.
    Said second control signal VAL2 is then delivered to the DCO oscillator in order to slave it in frequency in step E8.
    Furthermore, the invention is not limited to these modes of implementation and embodiments but embraces all the variants.
    For example, it is possible to carry out said modulo-type operation by modifying the depth of the cnt counter-divider and the ACC accumulator.
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    1. A method of contactless communication between an object (TG) and a reader (RD) using active load modulation, the method comprising synchronization between a first carrier signal (CLK) transmitted by the reader (RD) and having a reference frequency, and a second carrier signal (OUT) taken from the output signal (SIG4) of a controlled oscillator (DCO) of a digital phase locked loop (DPLL) of said object (TG), said synchronization comprising :
    as long as a locking of said loop (DPLL) has not been detected, a control of the frequency of the oscillator output signal (DCO), on a frequency multiple of the reference frequency, by controlling the oscillator (DCO) with a first control signal (VAL1) generated from a first value (ERR1) representative of the phase error of said phase locked loop (DPLL), and once said lock detected, a pursuit of the servo by controlling the oscillator (DCO) with a second control signal (VAL2) generated from a second value (ERR2) obtained by an operation of the modulo type performed on said first value (ERR1) representative of the 'phase error of the loop (DPLL).
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which said first value (ERR1) is a digital word comprising a first sequence of bits (SQ1), and in which said modulo type operation comprises a selection of least significant bits (PF) representing a second sequence (SQ2) of bits representative of said second value (ERR2).
    [3" id="c-fr-0003]
    3. Method according to claim 1 or 2, comprising prior to the control by said loop (DPLL), a masking and / or a multiplication of the frequency of the first carrier signal (CLK) by a mask and / or a multiplicative factor .
    [4" id="c-fr-0004]
    4. Method according to claim 3, in which the mask or the multiplicative factor is configurable.
    [5" id="c-fr-0005]
    5. Object (TG) capable of communicating without contact with a reader (RD) by active load modulation, comprising an input (2000) for receiving a first carrier signal (CLK) emitted by the reader (RD), an output (24) for delivering a second carrier signal (OUT) drawn from an output signal (SIG4) from a controlled oscillator (DCO) of a digital phase locked loop (DPLL), and synchronization means ( MSYNC) configured to synchronize said first carrier signal (CLK) and the second carrier signal (OUT), said synchronization means (MSYNC) comprising:
    detection means (MD) configured to detect the locking of said loop (DPLL);
    control means (MC) configured for, as long as the detection means (MD) have not detected the locking of said loop (DPLL), slaving the frequency of the output signal of the oscillator (DCO) to a frequency multiple of the reference frequency, by controlling the oscillator (DCO) with a first control signal (VAL1) generated from a first value (ERR1) representative of the phase error of said phase locked loop ( DPLL), and once the detection means (MD) have detected said locking, continue the servo control by controlling the oscillator (DCO) with a second control signal (VAL2) generated from a second value (ERR2 ) delivered by a first module (MD1) configured to perform an operation of the modulo type on said first value (ERR1) representative of the phase error of the loop.
    [6" id="c-fr-0006]
    6. Object (TG) according to claim 5, wherein said first value (ERR1) is a digital word comprising a first sequence of bits (SQ1), and wherein said first module (MD1) is configured to perform said operation by selecting least significant bits (PF) representing a second sequence of bits (SQ2) representative of said second value (ERR2).
    [7" id="c-fr-0007]
    7. Object (TG) according to claim 5 or 6, wherein the synchronization means (MSYNC) comprise a second module (MD2) configured to mask the frequency of the first carrier signal (CLK) by a mask prior to the slaving by said loop, and a third module (MF) configured to multiply the frequency of the first carrier signal (CLK) by a multiplying factor prior to slaving by said loop.
    10
    [8" id="c-fr-0008]
    8. Object (TG) according to claim 7, wherein the mask or the multiplying factor is adjustable.
    [9" id="c-fr-0009]
    9. Object (TG) according to one of claims 5 to 8, wherein the phase locked loop (DPLL) comprises a filter of proportional integral type (DF) configured to filter said first
    15 value (ERR1) representative of the phase error and said second value (ERR2) representative of the phase error.
    [10" id="c-fr-0010]
    10. Object (TG) according to one of claims 5 to 9, forming an emulated telephone in card mode.
    类似技术:
    公开号 | 公开日 | 专利标题
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    同族专利:
    公开号 | 公开日
    US10749719B2|2020-08-18|
    CN210780786U|2020-06-16|
    US20200099554A1|2020-03-26|
    EP3629487B1|2020-11-11|
    CN110943764B|2021-08-17|
    EP3629487A1|2020-04-01|
    FR3086476B1|2020-09-11|
    CN110943764A|2020-03-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20080100386A1|2006-10-27|2008-05-01|Christian Wicpalek|Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal|
    US20100039183A1|2008-08-15|2010-02-18|National Chiao Tung University|Digital fast-locking frequency synthesizer|
    EP2763076A1|2013-02-01|2014-08-06|Nxp B.V.|Wireless communications using active modulation|
    EP3276986A1|2016-07-27|2018-01-31|Stmicroelectronics Sa|Method of contactless communication between an objet, for example a card emulated mobile phone, and a reader by active load modulation|
    JP2833577B2|1996-04-02|1998-12-09|日本電気株式会社|Transmission device|
    US9094113B2|2013-03-15|2015-07-28|Qualcomm Incorporated|Apparatus and method for reducing phase noise in near field communication device signaling|
    US9014323B2|2013-08-30|2015-04-21|Nxp B.V.|Clock synchronizer for aligning remote devices|
    US9577718B2|2014-11-19|2017-02-21|Qualcomm Incorporated|Systems and methods for inductively coupled communications|
    US9712317B2|2015-02-17|2017-07-18|Avago Technologies General Ip Pte. Ltd.|Carrier synchronization appropriate for ALM NFC data transmission|
    EP3121755B1|2015-07-21|2019-03-13|STMicroelectronics International N.V.|Radio-frequency identification transponder and method for data transmission by means of radio-frequency identification technology|
    FR3086476B1|2018-09-25|2020-09-11|St Microelectronics Sa|QUICK SYNCHRONIZATION BETWEEN AN OBJECT AND A CONTACTLESS COMMUNICATING READER THROUGH ACTIVE CHARGE MODULATION|FR3086476B1|2018-09-25|2020-09-11|St Microelectronics Sa|QUICK SYNCHRONIZATION BETWEEN AN OBJECT AND A CONTACTLESS COMMUNICATING READER THROUGH ACTIVE CHARGE MODULATION|
    FR3102625B1|2019-10-28|2021-11-12|St Microelectronics Sa|NFC device emulated in card mode comprising a digital phase-locked loop, and corresponding communication method.|
    法律状态:
    2019-08-20| PLFP| Fee payment|Year of fee payment: 2 |
    2020-03-27| PLSC| Search report ready|Effective date: 20200327 |
    2020-08-19| PLFP| Fee payment|Year of fee payment: 3 |
    2021-08-19| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1858732|2018-09-25|
    FR1858732A|FR3086476B1|2018-09-25|2018-09-25|QUICK SYNCHRONIZATION BETWEEN AN OBJECT AND A CONTACTLESS COMMUNICATING READER THROUGH ACTIVE CHARGE MODULATION|FR1858732A| FR3086476B1|2018-09-25|2018-09-25|QUICK SYNCHRONIZATION BETWEEN AN OBJECT AND A CONTACTLESS COMMUNICATING READER THROUGH ACTIVE CHARGE MODULATION|
    US16/569,999| US10749719B2|2018-09-25|2019-09-13|Synchronization between an object and a reader contactlessly communicating by active load modulation|
    EP19197739.6A| EP3629487B1|2018-09-25|2019-09-17|Quick synchronisation between an object and a contactless reader communicating by active load modulation|
    CN201910906874.6A| CN110943764B|2018-09-25|2019-09-24|Synchronization between an object and a reader for contactless communication by active load modulation|
    CN201921596081.0U| CN210780786U|2018-09-25|2019-09-24|Object capable of contactless communication with a reader using active load modulation|
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